Oinonen Consulting
FPGA | SoC | ASIC design & verification consulting
Digital IC designer with strong experience in SoC development, digital logic design, verification, and FPGA implementation.
My background combines hands-on industry work in IC R&D with academic expertise in electronics and telecommunications.
Area of consulting: Digital design (VHDL / SystemVerilog), Verification (UVM), FPGA prototyping, Python tooling
About me
Jesse Oinonen
BSc. in Electrical Engineering
Ongoing MSc. studies in Electronics Design
Skills:
Digital IC design (VHDL, SystemVerilog)
SoC architecture & RISC-V development
FPGA design & prototyping (Vivado, hardware bring-up)
Verification & testbench development (UVM)
Programming: Python, C/C++
Vivado, Design Vision, VCS, QuestaSim, VS Code, Git
Strong problem-solving & system-level thinking
📧 jesse.oinonen25@gmail.com
LinkedIn Profile
OVER 1000+ HOURS of experience with digital design & verification
Experience
Industry experience
LG Electronics
Digital IC Engineer Trainee
01/2025 - 12/2025
Designed and implemented RTL functionalities for RISC-V based modules using VHDL and SystemVerilog. Developed and verified testbenches and testcases with UVM methodology in VCS and Verdi. Contributed to SoC-level digital design and verification across multiple projects. Utilized Python and C for verification automation, calibration software, and tooling. Worked extensively in a Linux environment with Git for version control. Focused on hardware design, verification, and thorough documentation for collaborative development.
Abloy
R&D Electronics Engineer Summer Trainee
06/2024 - 08/2024
Involved in prototype construction, design, and documentation, as well as breadboard design and implementation. Conducted electronics testing (DVT), troubleshooting, and environmental testing of electronics. Supported development projects, maintained electronics lab equipment, and contributed to the development of production testing methods and software design.
AspoComp
Electrical Tester
05/2023 - 08/2023
Physical electrical testing of the PCB's, repairing of PCB layers, measuring of impedance and capacitance.
Projects
RISC-V + AI accelerator Zynq Soc (Own project)
Currently under development. A compact, FPGA-based AI accelerator designed to offload compute-intensive operations from an RV32I core. Implements a systolic array architecture for efficient matrix and vector computations, enabling fast linear algebra and lightweight ML tasks. Controlled and sequenced by the RISC-V processor, providing seamless integration into the Zynq-7000 SoC.
RISC-V Space Applications (Bachelor's thesis)
Bachelor's thesis that examines the suitability of the RISC-V instruction set architecture for space applications in the evolving space technology industry, and its advantages compared to other closed instruction set architecture solutions.
I2S Audioport IP Design Project (University)
Designed and implemented an I2S audio output interface IP block as part of an SoC design course. Learned the complete IC design and verification flow from high-level modeling with SystemC to RTL design with SystemVerilog and VHDL. Gained experience with UVM-based verification, formal methods, logic synthesis, IC layout, and post-layout analysis.
Digital Design Project (University)
Modeled and verified a simple processor core using SystemVerilog as part of an IC design course. Got familiar with SystemVerilog and the design flow of digital IC design & verification
View my own projects on GitHub
Contact
📧 jesse.oinonen25@gmail.com
📍 Turku, Finland