Industry experience
University of Turku - Robotics & Autonomous systems
Research & Teaching Assistant
02/2026 -
Assisting in teaching and research activities including
supporting laboratory engineers and researchers in
instructional and laboratory-related tasks & organizing
and supervising labs, demos, and workshops.
Designed and developed laboratory exercises and lecture
materials for the M.Sc. course FPGA for Embedded
Systems where I gained hands-on experience with FPGA
development tools, including Xilinx Vivado, Vitis, and
logic analyzers.
LG Electronics
Digital IC Engineer Trainee
01/2025 - 12/2025
Designed and implemented RTL functionalities for RISC-V based modules using VHDL and SystemVerilog.
Developed and verified testbenches and testcases with UVM methodology in VCS and Verdi.
Contributed to SoC-level digital design and verification across multiple projects.
Utilized Python and C for verification automation, calibration software, and tooling.
Worked extensively in a Linux environment with Git for version control.
Focused on hardware design, verification, and thorough documentation for collaborative development.
Abloy
R&D Electronics Engineer Summer Trainee
06/2024 - 08/2024
Involved in prototype construction, design, and documentation, as well as breadboard design and implementation. Conducted electronics testing (DVT),
troubleshooting, and environmental testing of electronics. Supported development projects,
maintained electronics lab equipment, and contributed to the development of production testing methods and software design.
Aspocomp
Electrical Tester
05/2023 - 08/2023
Physical electrical testing of the PCB's, repairing of PCB layers, measuring of impedance and capacitance.
Projects
Zynq-7000 Hardware-Accelerated Networking Dataplane (Own project)
Currently under development.
A Linux-controlled (ARM PS) and FPGA-accelerated (PL) networking dataplane designed for deterministic high-throughput packet processing.
Implements an AXI-Stream–based processing pipeline with zero-copy DMA for low-latency data movement between PS and PL.
Includes a reusable observability IP for real-time measurement of throughput, latency, and error statistics, enabling performance-aware system design and verification.
RISC-V + AI accelerator Zynq Soc (Own project)
Currently under development.
A compact, FPGA-based AI accelerator designed to offload compute-intensive operations from an RV32I core.
Implements a systolic array architecture for efficient matrix and vector computations, enabling fast linear algebra and lightweight ML tasks.
Controlled and sequenced by the RISC-V processor, providing seamless integration into the Zynq-7000 SoC.
RISC-V Space Applications (Bachelor's thesis)
Bachelor's thesis that examines the suitability of the RISC-V instruction set
architecture for space applications in the evolving space technology industry,
and its advantages compared to other closed instruction set architecture
solutions.
I2S Audioport IP Design Project (University)
Designed and implemented an I2S audio output interface IP block as part of
an SoC design course. Learned the complete IC design and verification flow
from high-level modeling with SystemC to RTL design with SystemVerilog and
VHDL. Gained experience with UVM-based verification, formal methods, logic
synthesis, IC layout, and post-layout analysis.
QAM64 Demodulator Project (University)
Designed and implemented a QAM64 demodulator using C++ for high-level
synthesis (Catapult HLS), covering DSP components such as CORDIC-based
NCO, FIR/IIR filtering, adaptive equalization (LMS/CMA), and symbol slicing.
Conducted C++/SystemC simulation, RTL verification, and synthesis-driven
optimization to meet throughput and timing targets.
Digital Design Project (University)
Modeled and verified a simple processor core using SystemVerilog as part of
an IC design course. Got familiar with SystemVerilog and the design
flow of digital IC design & verification
View projects on GitHub
